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| rev 1 march 2007 www.semtech.com 1 XE1203F XE1203F 433 mhz / 868 mhz / 915 mhz low-power, integrated uhf transceiver general description the XE1203F is a single chip transceiver operating in the 433, 868 and 915 mhz license-free ism (industry scientific and medical) frequency bands. its highly integrated architecture allows for minimum external components while maintaining design flexibility. al l major rf communication parameters are programmable and most of them can be dynamically set. the XE1203F offers the excellent advantage of high data rate communication at rates of up to 152. 3 kbit/s, without the need to modify the number or parameters of the external components. the XE1203F is optimized for low power consumption while offering high rf output power and exceptional receiver sensitivity. the device is suitable for applications which have to satisfy either the europ ean (etsi-300-220) or the north american (fcc part 15) regulatory standards. truerf? technology enables a low Ccost external component count (elimination of the saw filter) whilst still satisfying etsi and fc c regulations. applications automated meter reading (amr) home automation and access control high-quality speech, music and data over rf applications requiring konnex-compatibility key product features rf output power: up to +15 dbm high reception sensitivity: down to C114 dbm (typical) low power consumption: r x = 14 ma; t x = 62 ma @15 dbm (typical) supply voltage down to 2.4v data rate from 1.2 to 152.3 kbit/s, nrz coding konnex-compatible operation mode 11-bit barker encoder/decoder on-chip frequency synthesizer with minimum frequency resolution of 500 hz continuous phase 2-level fsk modulation received data pattern recognition bit-synchronizer for incoming data/clock synchronization and recovery rssi (received signal strength indicator) fei (frequency error indicator) rohs green package ordering information part number temperature range package XE1203Fi063trlf -40 c to +85 c vqfn48
? semtech 2007 www.semtech.com 2 XE1203F table of contents 1 functional block diagram........................... ................................................... .....................................3 2 pin description.................................... ................................................... ..............................................4 3 electrical characteristics ......................... ................................................... ........................................5 3.1 absolute maximum operating ranges .................. ................................................... .............................5 3.2 specifications ..................................... ................................................... .................................................5 3.2.1 operating range.................................... ................................................... .............................................5 3.2.2 electrical specifications .......................... ................................................... ............................................5 4 general description ................................ ................................................... ..........................................7 4.1 the receiver section............................... ................................................... ...........................................7 4.1.1 lna & receiver modes............................... ................................................... ........................................8 4.1.2 demodulation chain ................................. ................................................... ...........................................8 4.1.3 demodulator........................................ ................................................... ................................................8 4.1.4 bit synchronizer................................... ................................................... ................................................9 4.1.5 the data and datain pins ........................... ................................................... ...................................9 4.1.6 pattern recognition block.......................... ................................................... .........................................10 4.1.7 rssi............................................... ................................................... ................................................... 10 4.1.8 frequency error indicator C fei.................... ................................................... ....................................12 4.2 the transmitter section............................ ................................................... ........................................13 4.2.1 transmitter ........................................ ................................................... ................................................13 4.2.2 barker encoder/decoder ............................. ................................................... ......................................15 4.3 the frequency synthesizer .......................... ................................................... ....................................17 4.3.1 clock output for external processor ................ ................................................... .................................17 5 serial interface definition and principles of opera tion ............................................... .................18 5.1 serial control interface ........................... ................................................... ..........................................18 5.2 configuration and status registers................. ................................................... ...................................20 5.2.1 the configswitch register.......................... ................................................... ......................................20 5.2.2 rtparam configuration register..................... ................................................... .................................22 5.2.3 fsparam configuration register ..................... ................................................... .................................23 5.2.4 swparam configuration register - switching paramete rs ................................................. .................24 5.2.5 dataout status register ............................ ................................................... .......................................25 5.2.6 adparam configuration register..................... ................................................... .................................25 5.2.7 pattern register................................... ................................................... ...............................................27 5.2.8 test registers and additional settings ............. ................................................... .................................28 5.3 operating modes.................................... ................................................... ...........................................28 5.3.1 standard power up sequence for the receiver and tra nsmitter ........................................... .................28 5.4 selection of the reference frequency ............... ................................................... .................................29 5.5 clock output interface ............................. ................................................... .........................................30 5.6 default settings at power-up ....................... ................................................... ......................................30 6 application information............................ ................................................... ......................................31 6.1 matching network of the receiver ................... ................................................... ...................................31 6.2 matching network of the transmitter................ ................................................... ..................................31 6.3 vco tank........................................... ................................................... ................................................34 6.4 loop filter of the frequency synthesizer........... ................................................... ..................................34 6.5 reference crystal for the frequency synthesizer .... ................................................... ...........................35 7 packaging information .............................. ................................................... .....................................36 ? semtech 2007 www.semtech.com 3 XE1203F the XE1203F is a single-chip uhf transceiver integr ated circuit intended for use as a low cost fsk tra nsceiver to establish a frequency-agile, half-duplex, bi-direct ional rf link, with nrz (non-return to zero) data c oding. barker encoder/decoder hardware can be activated to modula te/demodulate the transmitted signal to reduce the effects of fixed-frequency in-band interference. the device is available in a vqfn48 package and is designed to p rovide a fully functional multi-channel fsk transceiver. it is intended for applications in the 868 mhz europea n band and the north american 902-928 mhz ism band. the single chi p transceiver operates down to 2.4v and provides a low power solution for battery-operated and power sensi tive applications. the XE1203F is capable of operat ing data rates up to 152.3 kbit/s, making it ideally suited for applications where high data rates are required . 1 functional block diagram lna famp phase shifter lo_buf mmod divider vco pa ch pump pfd iref famp rfout tka tkb lfb rfa rfb divctl vco tank loop filter matching network matching network vddf vddd vddp vssf vssd vssp lpf lpf bbamp lim lim oscillator /n clock out demod pattern matching bbamp por iref modulator /n synthesizer fei bitsync xta xtb clkout tsupp tmod(3:0) por clkxtal vdd vdda vss vssa xtal 11 bits barker decoder pattern si dclk data datain xe1203 logic control 11 bits barker encoder rssi control data so sck en switch iamp qamp qamp iamp figure 1: XE1203F block diagram xe1203 truerf? ? semtech 2007 www.semtech.com 4 XE1203F 2 pin description pin name i/o description 1 n.c. not connected 2 n.c. not connected 3 n.c. not connected 4 vssf ground for the rf analog blocks 5 rfa in rf input 6 rfb in rf input 7 vssp ground for the rf power amplifier 8 vssp ground for the rf power amplifier 9 rfout out rf output 10 vddp power supply for the rf power amplifier 11 test pin in connected to ground 12 vddf power supply for the rf analog blocks 13 vssf ground for the rf analog blocks 14 tka in/out vco tank 15 tkb in/out vco tank 16 vssf ground for the rf analog blocks 17 lfb in/out loop filter of the pll 18 vddd power supply for the rf digital blocks 19 vssd ground for the rf digital blocks 20 test pin in connected to ground 21 test pin in connected to ground 22 n.c. not connected 23 test pin in connected to ground 24 test pin in connected to ground 25 vssa ground for the analog blocks 26 xta in/out crystal and input of external clock 27 vssa ground for the analog blocks 28 xtb in/out crystal 29 vdda power supply for the analog blocks 30 qamp buffered q output 31 iamp buffered i output 32 test pin in connected to ground 33 test pin in connected to ground 34 test pin in connected to ground 35 en in 3-wire interface communication enable signa l 36 vdd power supply for the digital blocks 37 switch in/out receiver or transmitter mode selec tion 38 so out data output of the 3-wires interface 39 si in data input of the 3-wires interface 40 sck in input clock of the 3-wires interface 41 clkout out output clock at quartz frequency divid ed by 4, 8, 16 or 32 42 vss ground for the digital blocks 43 dclk out transmitter or receiver clock 44 data in/out transmitter input data or receiver ou tput data 45 datain in transmitter input data 46 pattern out output of the pattern recognition block 47 n.c. not connected 48 n.c. not connected ? semtech 2007 www.semtech.com 5 XE1203F 3 electrical characteristics 3.1 absolute maximum operating ranges stresses above the values listed below in table 1 m ay cause permanent device failure. exposure to abso lute maximum ratings for extended periods may affect dev ice reliability. symbol description min. max. unit vddmax supply voltage -0.4 3.9 v ml receiver input level -5 dbm tmax storage temperature -55 125 c table 1: absolute maximum ratings the device is esd sensitive and should be handled w ith precaution. 3.2 specifications 3.2.1 operating range symbol description min. max. unit vdd supply voltage 2.4 3.6 v t temperature -40 85 c clop load capacitance on digital ports - 25 pf table 2: operating range 3.2.2 electrical specifications table 3 below gives the electrical specifications o f the transceiver under the following conditions: supply voltage vdd = 3.3v, temperature = 25 c, 2-l evel fsk without pre-filtering, carrier frequency f c = 915 mhz, frequency deviation d f = 55 khz, bit rate br = 4.8 kbit/s, base band fil ter bandwidth bbw = 200 khz, bit error rate ber = 0.1% (measured at the output of the bit synch ronizer), lna input and rf pa output matched to 50 w , environment as defined in section 6, unless otherwi se specified. symbol description conditions min typ max unit iddsl supply current in sleep mode - 0.2 1 ua iddst supply current in standby mode quartz oscillato r (39 mhz) enabled - 0.85 1.10 ma iddr supply current in receiver mode - 14 17 ma iddt supply current in transmitter mode (with optimum load-matching) rfop = 5 dbm rfop = 15 dbm - - 33 62 40 75 ma ma br = 4.8 kbit/s mode a (*1) br = 4.8 kbit/s mode b (*1) br = 32.7 kbit/s mode a (*1) br = 32.7 kbit/s mode b (*1) - - - - -114 -101 -109 -96 -111 -98 -106 -93 dbm dbm dbm dbm rfs rf sensitivity d f = 200 khz, bbw = 600 khz br = 152.3 kbit/s mode a (*1) br = 152.3 kbit/s mode b (*1) - - -101 -89 -98 -86 dbm dbm br = 1154 bit/s mode a (*1) - -113 -110 dbm rfsb rf sensitivity with barker coding/decoding enabled br = 1154 bit/s mode b(*1) - -100 -97 dbm fda frequency deviation programmable 1 - 255 khz ccr co-channel rejection -13 -10 - dbc ? semtech 2007 www.semtech.com 6 XE1203F symbol description conditions min typ max unit iip3 input intercept point f 1 = f lo + 1 mhz f 2 = f lo + 1.945 mhz mode a (*1) mode b (*1) -36 -21 -33 -18 - - dbm dbm bbw base band filter bandwidth dsb programmable (*2) - - 200 600 - - khz khz acr adjacent channel rejection funw = f lo + 650 khz pw= - 108dbm, mode a (*1) 45 48 - dbc br bit rate programmable 1.2 152.3 kbit/s rfop rf output power programmable rfop1 rfop2 rfop3 rfop4 -3 +2 +7 +12 0 +5 +10 +15 - - - - dbm dbm dbm dbm fr synthesizer frequency range programmable each range with its own external components 433 868 902 - - - 435 870 928 mhz mhz mhz ts_tr transmitter wake-up time from oscillator enabl ed - 150 250 us ts_re receiver baseband wake-up time from oscillator enabled - 0.5 0.8 ms ts_rssi rssi wake-up time from receiver enabled - - 1 m s ts_rssim rssi measurement time 0.5 ms ts_os crystal oscillator wake-up time fundamental 3 rd overtone - - 0.3 2.5 0.5 ms ms ts_fei fei wake-up time - - 2/br ms ts_sync_aq time for synchronization of the barker decoder input power of C106 dbm data rate = 1154 bits/s chip rate = 12.7 kcps from rx enabled - 5 - ms xtal crystal oscillator frequency fundamental or 3 rd overtone - 39 - mhz fstep frequency synthesizer step exact step is xtal / 77 824 - 500 - hz vthr rssi equivalent input thresholds mode a (*1) low range:vthr1 vthr2 vthr3 high range:vthr1 vthr2 vthr3 - - - - - - -100 -95 -90 -85 -80 -75 - - - - - - dbm dbm dbm dbm dbm dbm spr spurious emissions in rx mode (*4) - -65 - dbm sck serial clock frequency 1 mhz vih digital input level high (*3) % vdd 75 - - % vil digital input level low (*3) % vdd - - 25 % voh digital output level high % vdd 75 - - % vol digital output level low % vdd - - 25 % table 3: electrical specifications notes: (*1) mode a: high sensitivity mode; mod e b: high linearity mode. as defined in paragraph 4 .1.1. (*2) an intermediate bandwidth of 300 khz can also be selected by using additional settings described in section 5.2.8. (*3) throughout this document, digital signal level s are named high or 1, and low or 0. (*4) spr strongly depends on the design of the appl ication board and the choice of the external compon ents. values down to -70 dbm can be achieved with careful design. ? semtech 2007 www.semtech.com 7 XE1203F 4 general description the XE1203F is a direct conversion (zero-if) half-d uplex data transceiver. the circuit operates in thr ee different ism frequency bands (433 mhz, 868 mhz and 915 mhz) and uses 2-level fsk modulation/demodulation to pro vide a complete transmission link. it is capable of oper ating at data rates between 1.2 and 152.3 kbit/s, m aking it ideally suited for applications where high data rates are r equired. it also supports the konnex standard where the bit rate is 32.7 kbit/s. the device includes dedicated barker e ncoder/decoder hardware that may be activated to modulate/demodulate the transmitted signal to reduc e in-band interferences. the XE1203F is a highly programmable device C chann el, bit rate, frequency deviation, output power, ba se band filter bandwidth, sensitivity vs. linearity, rssi f eature, and many other parameters C which makes it extremely flexible, to meet a large number of end user requir ements. the main functional blocks of the XE1203F are the r eceiver, the transmitter, the frequency synthesizer and some service blocks. the device also includes a series o f configuration and status registers. in a typical application, the XE1203F is programmed by a microcontroller via the 3-wire serial bus si, so, sck to write to and read from these registers. the receiver converts the incoming 2-level fsk modulated signal into a synchronized bit stream. the transmitter performs the modulation of the carrier by an input bit stream and the transmission of the modulated signal. the frequency synthesizer generates the local oscillator (lo) signal for the receiver section as well as the continuous phase fsk modulated signal for the trans mitter section. the service blocks provide the internal voltage and current sources a nd provide all the necessary functions for the circuit to work properly. the configuration registers are a set of variable-length registers that are us ed to store various settings to operate the XE1203F transceiver circuit. they are l isted below in table 4. refer to section 5.2 for th e detailed descriptions of these registers. these registers ar e accessed in write or read mode through the 3-wire serial bus, as described in section 5.1. name description configswitch 1-bit data to switch between 2 sets of user-predefined swparam configuration registers rtparam receiver and transmitter parameters fsparam lo, bitrate, deviation and other frequency parameters swparam 2 sets of user-predefined configuration reg isters dataout status register which can be read through t he 3-wire serial interface adparam additional parameters pattern reference pattern for the pattern recognit ion feature table 4: configuration registers naming convention: throughout this document, each individual bit in a particular configuration register includes the name of this register followed by a bit identifier. for example, rtparam_band are the band bits with in the rtparam register. the digital interface provides internal control signals for the whole ci rcuit according to the configuration register settings. 4.1 the receiver section the receiver converts the incoming 2-level fsk modu lated signal into a synchronized bit stream. the re ceiver is composed of a low-noise amplifier, two down-convers ion mixers, two base band filters, two base band am plifiers, two limiters, a demodulator and a bit synchronizer. the bit synchronizer translates the output of the demodulator into a glitch-free bit stream available on the pin data. it also generates a synchronized clock, dclk, which can be ? semtech 2007 www.semtech.com 8 XE1203F used to sample the data signal without additional e xternal signal processing. in addition, the receive r includes a digital received signal strength indicator (rssi), a frequency error indicator (fei) that provides inf ormation about the local oscillator frequency error, and a pattern recognition function to detect preprogrammed seque nces in the received serial data stream. finally, a user-select able barker coding/decoding feature can be activate d to spread the outgoing data with an 11-bit barker code upon t ransmission and decode the incoming data upon recep tion by correlating the spread data with the 11-bit barker code. 4.1.1 lna & receiver modes the lna of the receiver has two programmable operat ion modes: the high sensitivity mode, mode a, for r eception of weak signals; and the high linearity mode, modxe b, for strong signals. the operation mode is defin ed by the contents of the swparam_rmode1 and swparam_rmode2 c onfiguration register bits. mode a : high sensitivity mode, approximately 13db better than in mode b (see 3.2.2, rfs parameter) mode b : high linearity mode, iip3 approximately 15db high er than in mode a (see 3.2.2, iip3 parameter) 4.1.2 demodulation chain the demodulation chain consists of an fsk demodulat or, bit synchronizer, barker decoder and a pattern recognition block. figure 2 below illustrates the i nteraction between each section of the demodulation chain. fsk demodulator barker decoder bit synchronizer pattern recognizer data control data dclk pattern pow pow pow rtparam_bitsync rtparam_barker rtparam_pattern data dclk data dclk fsparam_br adparam_psize adparam_ptol adparam_pattern data figure 2: demodulation architecture 4.1.3 demodulator the demodulator provides a demodulated data stream from the received fsk modulated base band limited s ignals, i_lim and q_lim. if the end-user application requir es direct access to the output of the demodulator, then the ? semtech 2007 www.semtech.com 9 XE1203F rtparam_bitsync and rtparam_barker configuration re gister bits are set low (disabled). in this case th e demodulator output is directly connected to the dat a pin and the dclk pin is set to low. otherwise, th e demodulator output is processed by the bit synchron izer. for correct operation of the demodulator the modula tion index b of the input signal should meet the following condition: ,2 2 3 = d br f b where d f is the frequency deviation and br the bit rate. 4.1.4 bit synchronizer the raw output signal from the demodulator usually contains jitter and glitches. the bit synchronizer transforms the data output of the demodulator into a glitch-free b it stream available on the data pin and generates a synchronized clock dclk to be used for sampling the data output (see figure 3, below). data(nrz) dclk figure 3: bit synchronizer timing diagram. to ensure the correct operation of the bit synchron izer, in addition to the requirement for the modula tion index defined in 4.1.3 above, the following conditions ha ve to be satisfied: a preamble of 24 bits is required for the synchron ization, the preamble must be a sequence of 0 and 1 sen t alternatively, during transmission of data, the bit stream must h ave at least one transition from 0 to 1 or from 1 to 0 every 8 bits. the accuracy of the bit rate must be better than 5%. the bit synchronizer is enabled when rtparam_bsync configuration register bit is high. if this bit set low, the bit synchronizer is disabled. in this case the output o f the demodulator is directed to the data pin and t he dclk output is set to 0. the received bit rate is defined by the value of th e fsparam_br configuration register, and is calcula ted as follows: bit rate = 1 0)) : m_br(6 int(fspara 3 34. 152 + e where int(x) is the integer value of the unsigned b inary representation of (x). note: for konnex standard operations, the bit rate is fixed at 32.7 kbit/s. adparam_enable_konnex shou ld be set to a 1. 4.1.5 the data and datain pins the pin data is by default used by both the transmi tter and the receiver sections. by default it is se t as a bidirectional i/o pin. when in receive mode, demodu lated data appears at data as an output signal. in transmit mode, the transmitted bit stream is applied to this pin as an input. some applications may require separate input and ou tput pins for the transmitted and received data. in this case the user has to set the adparam_disable_data_bidir configuration register bit to 1. as a result the data pin is set as an output only for the received data, while the transmit data is controlled via the datain input pi n. ? semtech 2007 www.semtech.com 10 XE1203F 4.1.6 pattern recognition block when in receiver mode, this feature is activated by setting rtparam_pattern configuration register bit high. the demodulated data signal is compared with a pattern stored in the patparam_pattern configuration regist er. the pattern output pin is driven by the output of this comparator and is synchronized by dclk. it is set t o high when a matching condition is detected, otherwise set to low. the pattern output is updated at the rising ed ge of dclk. the number of bits used for comparison is defined i n the adparam_psize configuration register and the number of tolerated errors for the pattern recognition is def ined in the adparam_ptol register. figure 4, below, illustrates the pattern matching process. figure 4: pattern matching operation. 4.1.7 rssi when enabled, this function provides a received sig nal strength indication based on the signal at the output of the base-band filter. to enable the rssi function, the rtparam_rssi configuration register bit should be s et to 1. when enabled, the status of the rssi in the dataout _rssi register is a 2-bit word which can be read vi a the serial control interface. the content of the register is d efined in table 5, below, where v rffil is the differential amplitude equivalent to the rf input signal with the receiver operated in a-mode. the thresholds, v th are the equivalent of the signal at the output of the base-band filter stage, divided by the signal gain. dataout_rssi description 0 0 v rffil vthr1 0 1 vthr1 < v rffil vthr2 1 0 vthr2 < v rffil vthr3 1 1 vthr3 < v rffil table 5 rssi status description two possible ranges, each having a set of three v th threshold values, vthr1, vthr2, and vthr3 (see 3.2 .2 for actual values), are selected with the rtparam_rssir configuration register bit. they provide an overal l rssi range of typically 25 db. the timing diagram of an rssi measurement is illust rated in the figure 5 below. when the rssi function has been activated, the signal strength is periodically meas ured and the result is stored in the register datao ut_rssi each time this dataout_rssi register is read via the 3-w ire serial interface. note that ts_rs is the wake-u p time required after the function has been enabled to ens ure that a valid reading of rssi is obtained. ? semtech 2007 www.semtech.com 11 XE1203F figure 5: rssi measurement timing diagram note on the dataout_rssi update : during a read sequence of the dataout_rssi status register, the saout_rssi signal is generated internally as illustrated in th e figure 6 below. it can be seen the value of the d ataout_rssi status register is updated upon transmission of the bit a0 on the si line. the maximum frequency of sc k during the read operation of the rssi value is 100 khz. figure 6: generation of saout_rssi en saout_rssi sck a(4) a(3) a(2) a(1) a(0) si d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) so hz hz xxx val1 val2 val3 val4 0 val5 val1 val4 xxx ts_rssi saout_rssi rssi_out /en rtparam_rssi dataout_rssi ts_rssim ? semtech 2007 www.semtech.com 12 XE1203F 4.1.8 frequency error indicator C fei when enabled this function provides an indication o f the frequency error of the local oscillator compa red with the received carrier frequency. for guaranteed operatio n of the fei function the following two conditions should be met: 1) the modulation index, b , should meet the following condition: ,2 2 3 = d br f b where: d f = frequency deviation of the modulated input sign al, br = input data bit-rate. 2) the bandwidth of the baseband filter (bbw) must be greater than the sum of the frequency offset and the received peak signal bandwidth, as defined below: bbw > f offset + bw signal where bbw is the baseband filter bandwidth defined by the rtparam_bw register. f offset is the difference between the carrier frequency and the lo frequency, and bw signal is equal to ?? ? ?? ? d + f br 2 . note on the timing for fei measurement: the timing diagram of the fei measurement process is illustrated in figure 7 below. as long as the fei function remains enabled, the frequency error is continuously measu red every 2/br seconds, starting ts_fei (see paragraph 3.2.2) after the fei function is enabled. the measurement results are loaded into the status registers dataout_msb_fe i and dataout_lsb_fei each time the dataout_lsb_fei register is read through the 3-wire serial interface. in the diagram below, saout_fei is generated internally d uring a read sequence from the dataout_lsb_fei status regist er. figure 7: timing diagram of the fei measurement proc ess the maximum frequency of sck during the fei read op eration is 100 khz. when using the konnex standard, the bit adparam_enable_konnex configuration register mu st be set to 1. first evaluation val1 val2 val3 0 val4 val1 val3 xxx ts_fei saout_fei fei_out en rtparam_fei dataout_msb_fei& dataout_lsb_fei 2/br val0 ? semtech 2007 www.semtech.com 13 XE1203F the frequency error can then be calculated by using the following formula: frequency error = (br/8)*int(dataout_fei(11:0)), where dataout_fei(11:0) = dataout_msb_fei(3:0) + da taout_lsb_fei(7:0), and int(x) is the integer value of the signed binary representation of x. 4.2 the transmitter section the transmitter performs the modulation of the carr ier by an input bit stream and the transmission of the modulated signal. carrier modulation is achieved directly thr ough the frequency synthesizer via a sigma-delta mo dulator. the frequency deviation and the bit-rate of the modulat ed carrier are programmable. an on-chip power ampli fier then amplifies the rf signal. the output power can be pr ogrammed with 4 possible settings: rtparam_tpow output power 0 0 rfop1 0 1 rfop2 1 0 rfop3 1 1 rfop4 table 6: output power settings 4.2.1 transmitter the transmit data should be applied to data or data in pins depending on the setting of the adparam_disable_data_bidir configuration bit. if th e parameter is set to 1, then the datain pin is u sed, otherwise the bidirectional pin data is used. the modulating signal on data or datain can be pre- processed before modulating the local oscillator to produce the outgoing fsk rf signal. this is the pre-filteri ng feature. the pre-filtering is selected by settin g the rtparam_filter configuration bit to 1. when rtpar am_filter is set to 1, the input baseband data is pre-filtered before being applied to the frequency synthesizer. this means that the rising and falling edge of each bit is linearly smoothed with a staircase transition. when rtparam_ filter is set to 0, the input baseband data is ap plied directly to the frequency synthesizer without any pre-filter ing function. the two possible modulation methods are shown in fi gure 8, where datain is the input bit stream from data or datain pins. ? semtech 2007 www.semtech.com 14 XE1203F figure 8: modulation with and without pre-filtering the main characteristic of this pre-filtering funct ion is the ratio between the rise/fall time to the bit duration, t rise /t bit . the value of this ratio can be programmed between t wo pre-defined values in the rtparam_stair configur ation bit, as shown in the table 7. rtparam_stair t rise /t bit 0 10% 1 20% table 7: t rise /t bit ratio when the pre-filtering function is enabled (rtparam _filter set to 1), only the following bit rates a nd frequency deviations can be used: fsparam_dev frequency deviation 00101000 00110111 01010000 10100000 11001000 40 khz 55 khz 80 khz 160 khz 200 khz no filtering staircase filtering datain or data in freq_synth in freq_synth ? semtech 2007 www.semtech.com 15 XE1203F fsparam_br bit rate (bit/s) 1111110 0111111 0011111 0001111 0000111 0000011 0000001 others (*) 1200 2400 4800 9600 19200 38400 76800 153000 table 8: possible bit rates and frequency deviations when pre-filtering is enabled (*) for any programmed value of fsparam_br which is not in the table 8 above, the data-rate is fixed t o 153 kbit/s and the pre-filtering is applied as defined by the user. if adparam_enable_konex is set high, then the pre-f iltering option is available for a bit rate of 32.7 kbit/s and one of the frequency deviations defined above. 4.2.2 barker encoder/decoder the barker encoder/decoder hardware can be activate d to modulate/demodulate the transmitted signal to reduce in-band interferences the barker decoder provides a n alternative to the bit synchronizer only for a fixed data rate of 1154bits/s . the barker block is selected when the rtparam_bar ker configuration bit is set to 1. in transmission, the information data at a bit rate of 1154bits/s is spread using an 11-bit barker code. the result is an encoded bit stream at 12.7 kilochips per second (kc ps), which is applied to the frequency synthesizer. on the receiver part, the signal is demodulated using the fsk demodulator (at 12.7 kcps) and then fed into th e barker decoder to recover the un-encoded data at 1154 bit/ s, together with a synchronized clock to sample it. figure 8 on the next page, illustrates the coding/decoding proc ess. figure 9: barker encoding and decoding channels. in receiver mode, the XE1203F provides a clock outp ut, dclk, to a microcontroller. the data can be sam pled at the rising edge of the clock. when using the barker decoding process, dclk is used to detect the sync acquisition. if there is no valid data, dclk remains high. the f irst falling edge of the clock means that the sync acquisition phase has been reached and that the output data is now available. this is illustrated below in figure 10. ? semtech 2007 www.semtech.com 16 XE1203F figure 10: data exchange during reception mode with barker the feature enabled when using the barker encoding in transmitter mode, the rtparam_barker parameter is set to 1 and the baseband data at 1154 bit/s is applied through eith er the data or datain depending to the status of adparam_disable_data_bidir. the data is spread into an encoded chip stream at 12.7 kcps by the barker encoder. this chip stream is directly applied to the frequen cy synthesizer without any pre-filtering. when using the barker coder/decoder feature in tran smission mode, the dclk pin is used to synchronize the data coming from a microcontroller or another source. th is dclk clock is generated by the XE1203F. at the f alling edge of the each clock a new data bit (on data or datain ) should be supplied by the microcontroller or anot her source. this data is sampled by the XE1203F at the next ris ing edge of dclk. it is then spread by using an 11- bit length barker code. the figure 11 shows the data exchange during the transmission mode when the barker featur e is enabled. information data from a microcontroller bit rate = 1154 bps dclk @1154 hz bit1 bit2 bit3 bit4 bit5 bit6 spread data @12.7 kchps bit0 spread bit0 spread bit1 spread bit2 spread bit3 spread bit4 spread bit5 figure 11: data exchange during transmission mode w ith the barker feature enabled ? semtech 2007 www.semtech.com 17 XE1203F 4.3 the frequency synthesizer the frequency synthesizer generates the local oscil lator (lo) signal for the receiver section as well as the continuous phase fsk (cpfsk) modulated signal for t he transmitter section. the core of the synthesizer is implemented with a sigma-delta pll architecture. th e frequency is programmable with a minimum step-siz e of 500 hz in the 433, 868 and 915 mhz frequency bands. thi s block includes a crystal oscillator which provide s the frequency reference for the pll. this reference fre quency can also be used as a reference clock for th e external microcontroller on the clkout pin. 4.3.1 clock output for external processor a reference clock can be generated by XE1203F for u se by an external microcontroller. the rtparam_clko ut configuration bit determines the status of the clko ut pin. when set high clkout is enabled, otherwise its disabled. the output frequency at clkout is defined by the value of the adparam_clkfreq parameter. the output frequency at clkout is the reference oscillator fre quency divided by 4, 8, 16 or 32. with the referenc e oscillator frequency at 39 mhz this provides a reference clock at 9.75 mhz, 4.87 mhz, 2.44 mhz or 1.22 mhz, respe ctively. this clock signal is disabled in sleep mode. ? semtech 2007 www.semtech.com 18 XE1203F 5 serial interface definition and principles of ope ration 5.1 serial control interface a 3-wire bi-directional bus (sck, si, so) is used t o communicate with the XE1203F. sck and si are inpu t signals supplied externally, for example by the microcontro ller. the XE1203F configures the so signal as an ou tput pin during read operation, and it is tri-stated in othe r modes. the falling edge of the sck signal is used to sample the si pin to write data into the internal shift register of the XE1203F. the rising edge of the sck signal i s used to output data to so pin by XE1203F, so the microcontroller s hould sample data at the falling edge of sck. the signal en must be low during the whole write an d read sequences. in write mode the content of the particular configuration register (see 5.2) is updated on the next rising edge of the en signal. before this risi ng edge, the new data is stored in temporary registers which do not affect the transceiver settings. the timing diagram of a write sequence is illustrat ed in figure 12 below. the sequence is initiated wh en a start condition is detected, defined by the si signal bei ng set to 0 during one period of sck. the next bi t is a read/write (r/w) bit which should be 0 to indicate a write o peration. the next 5 bits contain the address of th e configuration/status registers a[4:0] to be accesse d, msb first (see 5.2). then, the next 8 bits conta in the data to be written into the register. the sequence ends with 2 stop bits set to 1. the data on si should change on the rising edges of sck, and is sampled on the falling edge of sck. after the 2 stop bits, the data transfer is t erminated. the si line should be at 1 for at least one extra sck clock cycle before a new write or read sequence ca n start. this mode of operation allows data to be written into mu ltiple registers keeping the en line low. the maximum frequency of sck is 1 mhz, except as de fined above when reading the rssi or fei outputs, w here the maximum frequency of sck is limited to 100 khz. the minimum clock pulse width is 0.5 us. over the operating supply and temperature range, set-up and hold time for si on the falling edge of sck are 200 ns. the register at address 0 is one bit long. when wri ting this register, the sequence described above is valid except that only one data bit is required instead of 8. ho wever, if a single write procedure is used for all registers 8 data bits must be sent when writing at address 0, but only th e msb will be stored at address 0. the remaining 7 data bits must all be 1. figure 12: write sequence into configuration regist er figure 13 illustrates a write sequence at address z ero. a(4) a(3) a(2) a(1) a(0) d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) sck si /en so high impedance ? semtech 2007 www.semtech.com 19 XE1203F figure 13: write sequence into configuration regist er at address zero the time diagram of a read sequence is illustrated in figure 14 below. the sequence is initiated when a start condition is detected, defined by the si signal bei ng set to 0 during a period of sck. the next bit is a read/write (r/w) bit which should be 1 to indicate a read op eration. the next 5 bits are the address of the con trol register a[4:0] to be accessed, msb first. the data from the register is then output on the so pin. the data be come valid at the rising edges of sck and should be sampled at th e falling edge of sck. after this, the data transfe r is terminated. the si line must stay high for at least one extra sck clock cycle to start a new write or read sequence. the maximum current drive on so is 2 ma at a supply voltage of 2.7v and the maximum load is clop, as d efined in paragraph 3.2.2. when the serial interface is not used for read or w rite operations, both sck and si should be set to 1. except when in read mode, so is set to a high impedance mo de. figure 14: read sequence of configuration register when reading the register at address zero, the timi ng diagram is illustrated in figure 15. a(4) a(3) a(2) a(1) a(0) d(7) sck si /en so high impedance a(4) a(3) a(2) a(1) a(0) d(7) d(6) d(5) d(4) d(3) d(2) d(1) d(0) sck si /en so high impedance high impedance ? semtech 2007 www.semtech.com 20 XE1203F figure 15: read sequence of configuration register at address 0 5.2 configuration and status registers the XE1203F has several operating modes and configu ration parameters which can be programmed by the us er or the application. in addition, status information ma y be read from the circuit. some of the operating m odes, the status information and the configuration parameters are stored in a series of internal configuration a nd status registers that can be accessed by the microcontroll er through the 3-wire serial interface. there are seven variable configuration and status r egisters, as listed below in table 9. name description size (bits) address (binary format) configswitch 1-bit data to switch between 2 sets of user-predefined swparam configuration registers 1 x 1 00000 rtparam receiver and transmitter parameters 2 x 8 0 0001 - 00010 fsparam lo, bitrate, deviation and other frequency parameters 3 x 8 00011 - 00101 swparam 2 sets of user-predefined configuration registers 6 x 8 00110 - 01011 dataout status register which can be read through the 3-wire serial interface 2 x 8 01100 - 01101 adparam additional parameters 5 x 8 01110 - 10010 pattern reference pattern for the pattern recognition feature 4 x 8 10011 - 10110 table 9: configuration and status registers list all the bits that are referred to as reserved in this section should be set to 0 during write oper ations. 5.2.1 the configswitch register when operating the XE1203F, it might by useful to q uickly switch between two pre-defined operating mod es, to save time and traffic on the 3-wire serial interfac e bus. this may occur when the XE1203F is required to switch quickly between receive and transmit mode, when it has to operate on two different carrier frequencies , or when it has to switch between the high linearity mode b and the high sensitivity mode a. for that purpose, the five parameters stored in the swparam configuration regi ster are duplicated: the configuration set#1 and th e configuration set #2. a(4) a(3) a(2) a(1) a(0) d(7) sck si /en so high impedance high impedance ? semtech 2007 www.semtech.com 21 XE1203F depending on the configswitch 1-bit register or the input level at the switch pin, the XE1203F transce iver will use either the swparam configuration set#1 or the s et #2. if the rtparam_switch_ext configuration para meter is low, then the swparam configuration set is selected by the configswitch parameter C set#1 if configswi tch is 0, set#2 if configswitch is 1. if the rtparam_switch _ext configuration parameter is high, then the swpa ram configuration set is selected by the switch pin C s et#1 if switch is low, set#2 if switch is high. table 10 below summarizes the chip configuration pr ogramming: configswitch register switch pin rtparam_switch_ext configuration parameter swparam configuration set selected 0 switch is an output: 1 in transmitter mode 0 in the other modes 0 set #1: swparam_mode_1 swparam_power_1 swparam_rmode_1 swparam_t_delsig_in_1 swparam_freq_1 1 switch is an output: 1 in transmitter mode 0 in the other modes 0 set #2: swparam_mode_2 swparam_power_2 swparam_rmode_2 swparam_t_delsig_in_2 swparam_freq_2 x 0 1 set #1: swparam_mode_1 swparam_power_1 swparam_rmode_1 swparam_t_delsig_in_1 swparam_freq_1 x 1 1 set #2: swparam_mode_2 swparam_power_2 swparam_rmode_2 swparam_t_delsig_in_2 swparam_freq_2 table 10: configswitch, switch pin and swparam configur ation register by default the configuration set#1 is used and regi ster rtparam_switch_ext is set to 0. note that a new value of the configswitch register or at the switch pin should be modified when the en signal is low. the actual switch to the newly selected set of swparam register will be applied to the transceive r on the next rising edge of the en signal. ? semtech 2007 www.semtech.com 22 XE1203F 5.2.2 rtparam configuration register receiver and transmitter parameters name bits address description rtparam_bitsync 7 00001 bit synchronizer 0 -> disabled 1 -> enabled rtparam_barker 6 00001 barker coder/decoder: 0 -> disabled 1 -> enabled rtparam_rssi 5 00001 rssi function: 0 -> disabled 1 -> enabled rtparam_rssir 4 00001 rssi range: 0 -> low range (see 3.2.2) 1 -> high range (see 3.2.2) rtparam_fei 3 00001 fei function: 0 -> disabled 1-> enabled rtparam_bw 2 00001 baseband filter bandwidth (bbw) 0 -> 200 khz (dsb) 1 -> 600 khz (dsb) rtparam_osc 1 00001 reference frequency source: 0 -> internal crystal oscillator 1 -> external source rtparam_clkout 0 00001 clkout - reference frequency divided by 4,8,16,or 32: 0 -> disabled 1 -> enabled rtparam_stair 7 00010 transmitter pre-filter rise/f all time: 0 -> 10% of bit duration 1 -> 20% of bit duration rtparam_filter 6 00010 pre-filtering of the bit str eam in transmitter mode 0 -> no filtering 1 -> filtering the filtering function is available only for the fo llowing bit rates and frequency deviations: fspanam_br = "1111110" -> br = 1200 bit/s fspanam_br = "0111111" -> br = 2400 bit/s fspanam_br = "0011111" -> br = 4800 bit/s fspanam_br = "0001111" -> br = 9600 bit/s fspanam_br = "0000111" -> br = 19200 bit/s fspanam_br = "0000011" -> br = 38400 bit/s fspanam_br = "0000001" -> br = 76800 bit/s fsparam_dev = "00101000" -> d f = 40 khz fsparam_dev = "00110111" -> d f = 55 khz fsparam_dev = "01010000" -> d f = 80 khz fsparam_dev = "10100000" -> d f = 160 khz fsparam_dev = "11001000" -> d f = 200 khz rtparam_modul 5 00010 transmitter modulation: 0 -> enabled 1 -> disabled ? semtech 2007 www.semtech.com 23 XE1203F name bits address description rtparam_iqamp 4 00010 i&q amplifiers: 0 -> disabled 1 -> enabled rtparam_switch_ext 3 00010 swparam configuration se t selection: 0 -> configuration set defined by configswitch. swi tch is an output 1 -> configuration set defined by the pin switch. s witch is an input rtparam_pattern 2 00010 pattern recognition functio n: 0 -> disabled 1 -> enabled rtparam_band 1-0 00010 frequency band: 01 -> 433 C 435 mhz 10 -> 868 C 870 mhz 11 -> 902 C 928 mhz table 11: rtparam configuration register 5.2.3 fsparam configuration register lo, bitrate, deviation and other frequency paramete rs name bits address description fsparam_dev 7-0 00011 frequency deviation d f: d f =int( fsparan_dev) * 1 khz, where int(x) = integer value of the binary represen tation of x. example: 00000001 -> d f = 1 khz 11111111 -> d f = 255 khz fsparam_change_osr 7 00100 osr mode (oversampling r ate mode): 0 -> default bit rate defined by fsparam_br 1 -> variable osr fsparam_br 6-0 00100 bit rate (when "fsparam_chang e_osr = 0): br = 152340/(int(fsparam_br)+1), where int(x) = integer value of the binary represen tation of x. example: 0000000 -> br = 152.34 kbit/s 1111111 -> br = 1.19 kbit/s 0000100 -> br = 32.7 kbit/s used in konnex mode fsparam_osr 7-0 00101 define br in terms of fsparam _br and fs_param_osr: fsparam_osr = 00011101 and fsparam_change_osr = 1 for konnex standard table 12: fsparam configuration register ? semtech 2007 www.semtech.com 24 XE1203F 5.2.4 swparam configuration register - switching pa rameters the table below shows 2 sets of user-predefined con figuration registers. please refer to section 5.2 f or more details. name bits address description swparam_mode_1 7-6 00110 chip mode configuration se t#1: 00 -> sleep mode 01 -> stand by mode 10 -> receiver mode 11 -> transmitter mode swparam_power_1 5-4 00110 transmitter output power configuration set#1: 00 -> 0 dbm 01 -> 5 dbm 10 -> 10 dbm 11 -> 15 dbm swparam_rmode_1 3 00110 receiver mode configuration set#1: 0 -> mode a (high sensitivity) 1 -> mode b (high linearity) reserved 2-0 00110 reserved swparam_freq_1 7-0 7-0 00111 01000 lo frequency in 2s complement representation confi guration set#1: 000 -> flo = middle of the range 0xx-> flo = higher than the middle of the range 1xx-> flo = lower than the middle of the range see table 14 below swparam_node_2 7-6 01001 chip mode configuration se t#2: 00 -> sleep mode 01 -> stand by mode 10 -> rx mode 11 -> tx mode swparam_power_2 5-4 01001 transmitter output power configuration set#2: 00 -> 0 dbm 01 -> 5 dbm 10 -> 10 dbm 11 -> 15 dbm swparam_rmode_2 3 010001 receiver mode configuratio n set#2: 0 -> mode a (high sensitivity) 1 -> mode b (high linearity) reserved 2-0 01001 reserved swparam_freq_2 7-0 7-0 01010 01011 lo frequency in 2s complement representation confi guration set#2: 000 -> flo = middle of the range 0xx-> flo = higher than the middle of the range 1xx-> flo = lower than the middle of the range see table 14 below table 13: swparam configuration register the table following provides examples of lo frequen cy settings with fsparam_freq: ? semtech 2007 www.semtech.com 25 XE1203F swparam_freq_1 msb (byte address 00111) or swparam_freq_2 msb (byte address 01010) bit 7 bit 0 swparam_freq_1 lsb (byte address 01000) or swparam_freq_1 lsb (byte address 01011) bit 7 bit 0 resulting lo setting note: reference frequency = 39.0 mhz 00000000 00000000 f0, where f0 depends on the selected frequency band (see rtparam_band ) f0 = 434.0 mhz for the 433-435 mhz band f0 = 869.0 mhz for the 868-870 mhz band f0 = 915.0 mhz for the 902-928 mhz band 00000000 00000001 f0 + 500 hz 00000000 00000010 f0 + 2 * 500 hz 11111111 11111111 f0 C 500 hz 11111111 11111110 f0 C 2 * 500 hz table 14: examples of lo frequency settings 5.2.5 dataout status register status register which can be read through the 3-wir e serial interface name bits address description dataout_rssi 7-6 01100 rssi output: 0 0 -> lowest level, vthr1 0 1 -> 2 nd level, vthr1 ? semtech 2007 www.semtech.com 26 XE1203F name bits address description adparam_clk_freq 3-2 01110 clkout frequency (if ena bled) 00 -> 1.22 mhz (div ratio :32) 01 -> 2.44 mhz (div ratio :16) 10 -> 4.87 mhz (div ratio :8) 11 -> 9.75 mhz (div ratio :4) adparam_invert 1 01110 inversion of rx output data: 0 -> disabled 1 -> enabled adparam_regbw 0 01110 baseband filter bandwidth cal ibration: 0 -> enabled 1 -> disabled adparam_regfreq 7 01111 period of baseband filter b andwidth calibration whilst rx enabled: 0 -> only at start-up of the receiver 1 -> 60 seconds (default mode) or 7 seconds (test m ode) adparam_regcond 6 01111 baseband filter bandwidth c alibration as a function of selected bandwidth: 0 -> calibration restarted each time the bandwidth is changed 1 -> no calibration when the bandwidth is changed adparam_xsel 5 01111 selection of the xosc load cap acitance mode: 0 -> cl+c0 = 15 pf 1 -> cl+c0 = 11 pf, low current mode adparam_resxosc 4-1 01111 selection of the value of the shunt resistor across ports tka and tkb for a third overtone xtal operation: 0000 -> 3800 k w 0001 -> 2.55 k w 0010 -> 4.65 k w 0011 -> 1.78 k w 0100 -> 8.79 k w 0101 -> 2.07 k w 0110 -> 3.22 k w 0111 -> 1.56 k w 1000 -> 16.55 k w 1001 -> 2.26 k w 1010 -> 3.79 k w 1011 -> 1.66 k w 1100 -> 6.04 k w 1101 -> 1.91 k w 1110 -> 2.81 k w 1111 -> 1.48 k w adparam_enable_konnex 0 01111 konnex mode: 0 -> disabled 1 -> enabled adparam_chge_thres 7 10000 enable programming of th e sync and acquisition thresholds: 0 -> threshold are hard-coded and sync-loss counter is 50 bits 1 -> threshold are defined by bparam_sync_thres and bparam_trac_thres sync loss counter is variable and defined by adparam_sync_loss adparam_sync_thres 6:0 10000 barker mode sync acqui sition threshold adparam_disable_data_bidir 7 10001 data port bidire ctional mode: 0 -> enabled 1 -> disabled: data = output, datain = input adparam_trac_thres 6-0 10001 threshold for tracking barker mode adparam_fix_bsync 7 10010 bit synchronizer configur ation: 0-> default configuration 1-> high-interference environment ? semtech 2007 www.semtech.com 27 XE1203F name bits address description adparam_sync_loss 6-0 10010 number of bits before s ync loss detection for barker decoding algorithm table 16: adparam configuration register 5.2.7 pattern register this register holds the user supplied reference pat tern of 8, 16, 24, or 32 bits (see the adparam_psiz e parameter). the first byte of this pattern is always stored in the byte at address a[4:0] = 10011. if used, the 2 nd byte is stored at address a[4:0] = 10100, the 3 rd byte at address a[4:0] = 10101, and finally the 4 th byte at address a[4:0] = 01011. the msb bit of the reference pattern is always bit 7 of address 10011. comparing the demodulated data, the first bit recei ved of the last word is compared with bit 7 (the ms b) of byte address 10011. the last bit received is compared wi th bit 0 (the lsb) in the pattern register. name bits byte address description patparam_pattern 7-0 10011 10100 10101 10110 1 st byte of the reference pattern 2 nd byte 3 rd byte 4 th byte table 17: patparam pattern registers example of pattern recognition with a 32-bit patter n: byte address 10011 bit 7 bit 0 byte address 10100 bit 7 bit 0 byte address 10101 bit 7 bit 0 byte address 10110 bit 7 bit 0 10010011 10101010 10010011 10101010 101 10010011 10101010 10010011 10101010 previous bits from demodulator last bit received figure 16: example of pattern recognition with a 32- bit pattern example of pattern recognition with an 8-bit patter n: byte address 10011 bit 7 bit 0 byte address 10100 bit 7 bit 0 byte address 10101 bit 7 bit 0 byte address 10110 bit 7 bit 0 10010011 xxxxxxxx xxxxxxxx xxxxxxxx 101 10010011 previous bits from demodulator last bit received figure 17: example of pattern recognition with an 8- bit pattern ? semtech 2007 www.semtech.com 28 XE1203F 5.2.8 test registers and additional settings some settings in this 9-byte register can be used t o have access to additional configurations of the c ircuit. these settings are described in the table 18 below: name bits byte address description tparam_bw 3 10111 baseband filter bandwidth (dsb): 0 -> default values defined by rtparam_bw (200 and 600 khz) 1 -> 300khz tparam_hpf 1-0 10111 ssb cut-off frequency of the h pf stage (for cancellation of dc and low-frequency offsets in the baseband circuit): 00 -> 4.3 khz 01 -> 8.7 khz 10 -> 17.3 khz 11 -> 34.6 khz table 18: test registers and additional settings 5.3 operating modes the XE1203F has four main operating modes illustrat ed in table 19 below. these modes are defined by the content of the swpar am_mode_1 parameter when configuration set #1 is selected, or by the content of the swparam_mode_2 p arameter when configuration set #2 is selected. see also section 5.2.1. mode swparam_mode1(1:0) swparam_mode_2(1:0) description sleep mode 0 0 - standby mode 0 0 quartz oscillator enabled receiver mode 1 0 quartz oscillator, frequency synt hesizer, receiver enabled transmitter mode 1 1 quartz oscillator, frequency s ynthesizer, transmitter enabled table 19: XE1203F operating modes 5.3.1 standard power up sequence for the receiver a nd transmitter the XE1203F circuit can be switched between any con figuration by using the 3 wire interface (configswi tch) or by using the pad switch. this section describes the sw itching sequence of the chip. figure 18 shows the t ransition sequence from sleep mode to receiver mode via stand by mode. ? semtech 2007 www.semtech.com 29 XE1203F figure 18: mode transition 5.4 selection of the reference frequency the reference clock used by the frequency synthesiz er and internal digital circuit can be generated in ternally by connecting an external crystal between xta and xtb, or provided by an external oscillator. when using an external source, the signal should be applied to port xta an d the rtparam_osc configuration bit should be set t o 1. programmed mode programmed mode programmed mode programmed mode en actual mode en actual mode sleep -> stand_by -> receiver sleep -> stand_by -> transmitter en actual mode transmitter -> receiver en actual mode receiver -> transmitter ts_os ts_re ts_os ts_tr ts_tr sleep sleep sleep stand_by stand_by stand_by stand_by transmitter transmitter sleep receiver receiver receiver transmitter receiver transmitter transmitter transmitter receiver receiver ts_re ? semtech 2007 www.semtech.com 30 XE1203F the XE1203F can be used with a 39 mhz crystal opera ting in fundamental mode or in 3 rd overtone mode. for third overtone operation, an internal resistor to be swit ched across the crystal terminals xta and xtb is re quired. this resistor can be selected by programming the adparam _resxosc(3:0) parameter. the required value depends on the overtone crystal specification. when using 3 rd overtone mode, the user should be aware that durin g its power up the XE1203F oscillator will attempt to start at the fundamental frequency of th e crystal. it will only switch to the overtone mode when properly programmed through the 3-wire interface bus. as a r esult, if a microcontroller uses the XE1203F clkout as a clock source it is advisable to allow the oscillato r frequency to settle before undertaking any time o r timing sensitive operations. for fundamental mode operation, the adparam_resxosc (3:0) parameter is set to the default value of 000 0. this switches a 3.8 m w resistance across the crystal terminals. 5.5 clock output interface when register rtparam_clkout is set to 1 , the reference frequency is divided by 4, 8, 16 or 32, d epending on the value of the register adparam_clkfreq, and pr ovides a reference signal at clkout for a microcont roller or external circuitry. if the reference frequency is 3 9 mhz, then the output frequency available at clkou t is as defined in table 20 below: adparam_clkfreq clkout frequency 00 1.22 mhz 01 2.44 mhz 10 4.87 mhz 11 9.75 mhz table 20: clock output frequency selection when the XE1203F is in sleep mode, clkout is disabl ed even if rtparam_clkout remains high. 5.6 default settings at power-up the internally generated power-on-reset signal sets the rtparam, fsparam, adparam and pattern register s to the 00hex value. there is one important exception for clkout. although the rtparam_clkout is set to 0 at power-on reset, meaning the feature should be disabled, the XE1203F will generate a clkout signal after a power-on res et to provide a clock signal to a possible microcontrolle r connected to it. after a power-on reset, clkout w ill be the lowest available frequency, e.g. 1.22 mhz with a 39 mhz reference frequency. then, on the first rising edge of the /en signal C for example after a programming sequen ce via the 3-wire interface bus - the content of th e configuration registers will be updated. if the rtp aram configuration register has not been programmed during this first sequence after a power-on reset, the clk out clock signal will be disabled. it is strongly a dvised to initialize the rtparam_clkout parameter appropriate ly during the first programming sequence after a po wer-on reset, especially if an external microcontroller do es use this clkout clock signal to operate. it is recommended to initialize the XE1203F registe rs immediately after power-up. ? semtech 2007 www.semtech.com 31 XE1203F 6 application information this section provides details of the recommended co mponent values for the frequency dependant blocks o f the XE1203F. note that these values are dependent upon circuit layout and pcb structure, and that decoupli ng components have been omitted for clarity. 6.1 receiver matching network the schematic of the matching network at the input of the receiver is given below in figure 19 (for a source impedance of 50 w ). rfb rfa xe1203 cr3 cr2 cr1 source lr1 figure 19: receiver matching network the typical recommended values for the external com ponents are shown in table 21: name typical value for 434 mhz typical value for 868 mhz typical value for 915 mhz tolerance cr1 1.5 pf 1.5 pf 1.0 pf 5% cr2 1.5 pf 1.2 pf 1.0 pf 5% cr3 nc nc nc 5% lr1 100 nh 27 nh 27 nh 5 % table 21: typical component values for the matching network 6.2 transmitter matching network the optimum load impedances for 15 dbm output power at the three main frequencies are shown in table 2 2: 434 mhz 868 mhz 915 mhz pa optimum load 102 C 12j 78 + 19j 83 + 18j table 22: optimum load impedances for 15 dbm output power the smith charts in figure 20, figure 21, and figur e 22 below show contours of output power versus loa d impedance when the highest transmit level is select ed, i.e. 15 dbm: ? semtech 2007 www.semtech.com 32 XE1203F figure 20: output power vs. load impedance at 434 m hz figure 21: output power vs. load impedance at 868 m hz 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.8 0.6 1.2 1.6 2 3 0.6 0.8 1 1.2 1.6 2 3 868 mhz C 15 dbm 15 dbm 14 dbm 12 dbm 0 1 0.1 0.2 0.3 0.5 1 1.4 2 434 mhz C 15 dbm 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.8 0.6 1 1.2 1.6 2 3 0.6 0.8 1 1.2 1.6 2 3 15 dbm 14 dbm 12 dbm 0 0.1 0.2 0.5 1 1.4 0.3 ? semtech 2007 www.semtech.com 33 XE1203F figure 22: output power vs. load impedance at 915 m hz the schematic of the recommended matching network a t the output of the transmitter is shown in figure 23 below. the two p -sections are used to provide harmonic filtering in order to satisfy fcc and etsi regulations. figure 23: transmitter output network vdd lt3 c t5 c t4 c t2 lt2 lt1 c t1 XE1203F 915 mhz C 15 dbm 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.8 0.6 1 1.2 1.6 2 3 0.6 0.8 1 1.2 1.6 2 3 15 dbm 14 dbm 12 dbm 0 0.1 0.2 0.5 1 1.4 0.3 2 c t3 ? semtech 2007 www.semtech.com 34 XE1203F the typical component values of this matching circu it are shown below in table 23: name typical value for 434 mhz typical value for 868 mhz typical value for 915 mhz tolerance ct1 6.8 pf 1.5 pf 1.8 pf 5% ct2 1.0 pf 0.56 pf nc 5% ct3 22 pf 15 pf 33 pf 5% ct4 6.8 pf 3.3 pf 3.3 pf 5% ct5 4.7 pf 2.2 pf 2.2 pf 5% lt1 33 nh 39 nh 47 nh 5% lt2 22 nh 10 nh 10 nh 5% lt3 22 nh 8.2 nh 8.2 nh 5% table 23: typical component values for the recommen ded matching network at the output of the transmitt er 6.3 vco tank the tank of the vco is implemented with one inducto r in parallel with one capacitor. the characteristi cs of these two components must be as follows: name typical value for 434 mhz typical value for 868 mhz typical value for 915 mhz tolerance cv1 1.0 pf nc nc 5 % lv1 33 nh 8.2 nh 6.8 nh 2 % table 24: vco tank external components 6.4 loop filter of the frequency synthesizer the loop filter of the frequency synthesizer is sho wn in figure 24 below: cl2 xe1203 lfb rl1cl1 figure 24: loop filter of the frequency synthesizer XE1203F ? semtech 2007 www.semtech.com 35 XE1203F the values recommended for applications using bit r ates up to 38.4kbit/s are given in table 25 below: name typical value for 434 mhz typical value for 868 mhz typical value for 915 mhz tolerance cl1 22 nf 22 nf 22 nf 5% cl2 1.2 nf 1.2 nf 1.2 nf 5% rl1 560 w 470 w 470 w 5% table 25: typical loop filter values for bit rates up to 38.4 kbit/s the values recommended for applications using bit r ates higher than 38.4 kbit/s are given in table 26 below: name typical value for 434 mhz typical value for 868 mhz typical value for 915 mhz tolerance cl1 3.3 nf 4.7nf 4.7 nf 5% cl2 220 pf 330 pf 330 pf 5% rl1 1.2 k w 1 k w 1 k w 5% table 26: typical loop filter values for bit rates higher than 38.4 kbit/s 6.5 frequency synthesizer reference crystal for narrow band applications, where the lowest freq uency deviation and the narrowest baseband filter a re selected, the crystal for reference oscillator of the frequen cy synthesizer should have the following typical ch aracteristics: name description min. value typ. value max. value fs nominal frequency - 39.0 mhz (fundamental) - cl load capacitance for fs (on-chip) - 8 pf (*) - rm motional resistance - - 40 w cm motional capacitance - - 30 ff c0 shunt capacitance - - 7 pf (*) d fs(0) calibration tolerance at 25 c - - 10 ppm d fs( d t) stability over temperature range (-40 c to 85 c) - - 10 ppm d fs( d t) aging tolerance in first 5 years - - 5 ppm table 27: crystal characteristics (*) the on-chip oscillator mode is user-defined by programming adparam_xsel parameter: the first for c l = 8 pf and c0 = 7pf, and the second for cl = 8 pf and c0 = 3 pf; the latter will allow higher amplitude for t he internal signal with a slightly lower consumption. the electrical specifications given in section 3.2. 2 are valid for a crystal having the specifications given in table 27. for wide band applications requiring less frequency stability, the values for d fs(0), d fs( d t), and/or d fs( d t) can be relaxed. in this case foffset + bwssb should be low er than bwfilter, where foffset is the offset (erro r) on the carrier frequency (the sum of d fs(0), d fs( d t), and/or d fs( d t)), bwssb is the single side-band bandwidth of the signal, and bwfilter is the single side-band bandwidth of the b ase-band filter. the overtone crystal usage may result in higher osc illator start-up time than fundamental mode. the ov ertone crystal should be designed for cload = 8 to 10 pf a nd has parameters of rm < 60 w , c0 < 7 pf. ? semtech 2007 www.semtech.com 36 XE1203F 7 packaging information XE1203F is available in a 48-lead vqfn rohs green p ackage as shown in figure 25 below. please note that the exposed die pad should be conn ected to ground figure 25: package dimensions contact information ? semtech 2007 all rights reserved. reproduction in whole or in par t is prohibited without the prior written consent o f the copyright owner. the information presented in this document does not for m part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability wil l be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual propert y rights. semtech. assumes no responsibility or liability whatsoever f or any failure or unexpected operation resulting fr om misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life-support applications, devices or systems or other critical appli cations. inclusion of semtech products in such applications is understood to be undertaken sol ely at the customers own risk. should a customer purchase or use sem tech products for any such unauthorized application , the customer shall indemnify and hold semtech and its of ficers, employees, subsidiaries, affiliates, and di stributors harmless against all claims, costs damages and attorney fees which could arise. truerf? is a semtech trademark . semtech corporation advanced communications and sensing products divisi on 200 flynn road, camarillo, ca 93012 phone (805) 498-2111 fax : (805) 498-3804 |
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